In the semiconductor industries, strong efforts are made to bring a new promising memory technology based on non-volatile MRAM cells into practical use. An MRAM cell includes a stacked structure of magnetic layers separated by a non-magnetic tunneling barrier layer or conductive barrier. With a non-magnetic tunneling barrier layer, a magnetoresistive tunnel junction (MTJ) memory cell is formed. With a conductive barrier, a giant magnetoresistive memory cell is formed. Here, and in agreement with conventional reading in the art, both alternatives are referred to as “a magnetoresistive junction.”
In MRAM cells, digital information is not maintained by power as in conventional DRAMs, but rather by directions of magnetization in the ferromagnetic layers. More specifically, in an MRAM cell, magnetization of one ferromagnetic layer (“reference layer” or “pinned layer”) is magnetically fixed or pinned, while magnetization of the other ferromagnetic layer (“free layer”) is free to switch between two preferred directions along an axis of magnetization thereof. The axis of magnetization is typically parallel to the reference layer fixed magnetization.
Depending upon the magnetic orientation of the free layer, an MRAM cell exhibits two different resistance values in response to a voltage applied across the MRAM cell, wherein the resistance thereof is “low” when magnetizations are in parallel alignment and “high” when magnetizations are in anti-parallel alignment. Accordingly, logic values (“0” and “1”) may be assigned to different magnetizations of the free layer and detection of electric resistance provides the logic information stored in the magnetic memory element. An MRAM cell is typically written to by applying magnetic fields created by bi- or uni-directional currents that run through conductive lines operatively located adjacent the MRAM cell so that magnetic fields thereof can be coupled to the free layer magnetization.
In accordance with the well-known standard CMOS process for manufacturing MRAMs, upon a silicon or other suitable substrate provided with active substrate devices, such as transistors, typically, a tri-layered structure including a ferromagnetic bottom layer, a conductive or non-conductive intermediate layer, and ferromagnetic bottom layer, is deposited on dielectric material, followed by depositing a hard mask, patterning thereof, and etching of the tri-layered structure to produce magnetoresistive junctions, such as magnetoresistive tunnel junctions (MTJs).
However, in such conventional manufacturing of magnetoresistive memory elemens, etching of the tri-layered structure may be accompanied by deposition of polymer residuals on the side walls of the future magnetoresistive junctions. Such polymer residuals may cause severe problems, such as a hard fail (short) or interlevel short (MT to MA). Hence, removal of the polymer residuals is desirable, but likely to destroy the magnetoresistive junction. Therefore, at present, removal of polymer residuals is avoided.
An improved method of manufacturing MRAM cells where magnetoresistive junction can be formed without having problem as to polymer residuals is desirable.